Design of Efficient Matrix Multiplication Processing Elements in Systolic Arrays using Shift and Bit Dependent Conditional Add Approach

Real-time applications like audio signal processing and wireless communication highly demand the need for powerful and efficient multiplier and accumulator units (MACs) for achieving high performance. The overall system performance is closely correlated with the power, performance, and area (PPA) of the MAC unit. This paper proposes a novel modified Shift and Add (mSAC) architecture to perform the MAC operations. The mSAC cells serve as the processing elements (PE’s) of a systolic array. The proposed architecture’s credibility is verified with two design examples based on the simulations performed on Cadence Xcelium simulator and the hardware implementation has been done on the Cadence Genus Synthesis solution at a clock frequency of 2 GHz. The proposed hardware model achieves a lower power and area profile compared to state-of-the-art architectures.