A Multi-terminal Silicon Carbide Power Module with Low Parasitic Inductance

Parasitic inductance reduction in the SiC power module is a crucial aspect in power module design, which can help to decrease energy losses and improve the module’s efficiency. This paper proposes an innovative layout for 1200V SiC MOSFET half-bridge power module to lower the parasitic inductance within the power loop and the thermal resistance. Through an extensive evaluation of how upper and lower bridge chip distances affect parasitic inductance and thermal resistance, an optimal chip spacing is selected. Following double pulse experimental test, the fabricated module is benchmarked against a same current rating commercial 1200V SiC MOSFET half-bridge module, exhibits superior switching performance.