A Novel Axisymmetric SiC MOSFET Multichip Module with Staggered Terminals Design for Lowing Current Imbalance and Parasitic Inductance

SiC MOSFET power modules are widely recognized and used in high frequency and high power density power conversion system. However, the uneven current sharing among paralleled chips limits the current rating of the multichip power module. To address this challenge, this paper proposes a novel axisymmetric layout for SiC MOSFET multichip modules, where each power loop is physical and electrical symmetry in their layouts. This arrangement ensures balanced parasitic inductance for each power loop and gate loop, resulting in balanced current sharing within the power module. Furthermore, an improved Staggered power terminal layout design is introduced, reducing the total inductance of the power module from 2.97nH to 2.46nH. Compare with commercial module, the parasitic inductance of the proposed SiC module has been reduced by 0.51nH, a decrease of 55%. The turn-off loss of the proposed module is 53µJ, which is 53% lower compared to the commercial module with a turn-off loss of 114µJ.