Influence of Temporary Rigid Carrier Structure on Warpage during Wafer/Panel level packaging

Glass based rigid carriers are now essential for building present-day high-performance semiconductor packages with Package on Package (PoP), chiplets, stacked 2D ~ 3D structures as well as with organic interposer designs. High density RDL structures of these advanced packages are supported on these rigid carriers and exposed to mechanical handling, harsh chemicals, and temperature excursions during different steps of assembly processes. These package assemblies are performed on large size carriers, in wafer and panel formats.Besides providing a rigid support to the assembled structure, another important requirement for these carriers is to have a debonding (or releasing) capability from the packaged structure after completion of assembly. Bonding/debonding polymer materials are applied on the carrier top for this purpose. Currently laser-lift-off (LLO) technique is commonly used for debonding. As a result, choice of the carrier material is restricted to borosilicate glass only – which allows for laser ablation.Due to thermal stresses during different stages of the assembly process, the resulting composite materials at each stage of assembly cause warpage of the packaged structure ~ affecting process yield and limiting high density RDL formations. Efforts to understand and optimize this warpage issue are currently limited by ‘single carrier type and debonding/release layer’ materials.This paper introduces "a choice of carrier materials with an inorganic release layer" to overcome present constraints and minimize assembly warpage. The properties of the carrier material and its dimensions, viz. Coefficient of Thermal Expansion (CTE), thickness, modulus, and thermal conductivity, influence warpage. The influence of carrier materials on warpage has been studied.During chip-last Wafer/Panel level packaging, RDL is the first step in processing, where composite layers of photo imageable dielectric polymer (PID) and copper trace are formed on the carrier. In the next step the chips are mounted. While curing each layer of RDL, this composite structure is subjected to stresses causing warpage. As more number of layers are added, the magnitude of warpage keeps increasing. If not controlled, it could lead to alignment errors during lithography, thus limiting processing of complex multi-layer RDL structures with fine geometry. Further, warpage after RDL formation significantly impacts the chip placement & mounting process ~ causing assembly yield loss. Considering this as the most critical step and the foundation of wafer & panel level packages, this paper focuses on understanding the influence of different carrier substrate types with inorganic release layers on warpage during RDL process.Finite element analysis (FEA) had been used to simulate warpage in assembly during RDL formation. The purpose of this exercise is to provide solutions to mitigate warpage by selecting carrier substrate types with inorganic release layers.