Implementation of a Compensated Two-Stage Operational amplifier

Enormous growth is being noticed in the usage of hand-held electronic gadgets during the past decade. One of the very vital circuits in the implementation of these wireless communication systems is the high speed complementary metal oxide semiconductor (CMOS) operational amplifiers. Improvements and modifications in integrated circuit fabrication technologies along with state of the art novel circuit design methodologies have made the high speed low power linear circuits to offer better performance in terms of operating speed, noise free, power dissipation, signal to noise distortion, voltage gain and oscillation free. The work in this paper reports a low power CMOS two-stage operational amplifier with proper designed miller compensation technique. The technique uses a nulling resistor method and achieves temperature insensitive tracking method. Circuit simulation is carried out at CMOS 90nm in analog design environment of cadence tools software. The circuit simulation demonstrates a gain of 78dB, unity gain bandwidth of 194MHz, phase margin of 72 degrees, slew rate of 62.6V/µS, a power consumption of 106.3 microwatts and all the results confirm an improved performance when compared to the previous works in the literature.