A 3.5GHz Reconfigurable 2-Stage Cascode CMOS LNA with HPF Noise Matching & Body Bias for 5G NR n78 Band Applications

This paper presents a reconfigurable 2-stage cascode Low Noise Amplifier (LNA) designed for the 3.5 GHz 5G NR band (n78), implemented in UMC
$0.18 \mu \mathrm{m}$
-CMOS. The 2-stage cascode topology is selected for its high gain, while body-biasing technique optimizes linearity. It can dynamically switch between High Gain (HG) and High Linearity (HL) modes by adjusting bias voltages, accommodating both weak (HG) and strong (HL) signals, thus ensuring a wider dynamic range. To reduce Noise Figure (NF), the LNA employs a High Pass Filter (HPF) noise-matching structure in both stages as well as a high-Q external input matching network. Simulated results exhibit a 19.8 dB peak gain at 3.21 GHz (17.11 dB at 3.5 GHz) and a minimum NF (NFmin) of 3.46 dB (HG). At 3.5 GHz, it achieves an Input Third Order Intercept Point (IIP3) of 10.64 dBm and an Input 1-dB Compression Point (IP1dB) of −8.712 dBm (HL). At a 1.1V supply, the DC power is 14.4mW (HG) and 15.08mW (HL). Comparison with literature shows superior gain (HG) and linearity (HL), and a competitive NF and DC power, making this LNA design a promising choice for 5G applications.