Energy Efficient Accurate and Approximate Modified Adders for Ternary Multipliers

This paper presents energy-efficient approximate multiplier designs using proposed modified adder designs. In this paper, we propose accurate and approximate designs of modified half adder and full adders, MHA, FA
1
and FA
2
designed using a combination of 3×1 and 2×1 multiplexers. The proposed designs were simulated using the Synopsys HSPICE using MOSFET-like CNFET. The proposed modified half-adder consumes 63.2% less energy than the conventional half-adder. The proposed modified full adders FA
1
and FA
2
, respectively have a savings of 24% and 44% energy than the conventional full adder. The overall approximate multiplier saves 26% of energy than the conventional full adder-based multiplier. The applications of the proposed multipliers explored in image processing applications, such as image multiplication and the proposed approximation lead to better Peak signal-to-noise ratio (PSNR) and structural similarity index measure (SSIM) over the best existing designs.