A Semi-Folded Based High-Power-Efficiency FFT for Frequency Offset Estimate

Frequency offset estimate (FOE) is utilized to correct the incremental phase deviation caused by transceiver local oscillator mismatches, and determine the performance of the successive carrier offset compensation module. The FFT-based FOE method offers stability and controlled precision. However, as the FFT scale increases, the algorithm’s complexity also rises, which hinders real-time implementation of high-precision FOE hardware. While several research efforts aim to simplify the algorithm, there is limited focus on hardware implementation. In this paper, we introduce a semi-folded 256-point FFT with 64-way parallelism. By reusing the 64-point FFT module, computations are completed within four clock cycles, resulting in circuit area and power savings. We further leverage the semi-folded FFT structure to implement the FOE circuit. The experiments demonstrate that under the 28nm process technology, the semi-folded FFT achieves an area efficiency of 0.0043/(mm
²
/GS) and a power efficiency of 2.44mW/GS when working at a frequency of 714MHz. Additionally, when working at 500MHz the semi-foleded based FOE circuit has an area of 0.787mm
²
and a power consumption of 319.1mW, meets the requirements of a 256Gbps 16QAM communication system.