A 10b 400MS/s 2x-Time-Interleaved 2-Then-1b/Cycle SAR ADC in 90nm CMOS

This paper presents a 10-bit two-channel time-interleaved successive-approximation-register (SAR) analog-to-digital converter (ADC) to achieve a maximum sampling rate of 400 MHz in 90-nm CMOS. The channel-ADC incorporates a 2b/cycle-assisted SAR architecture to effectively speed up its operation speed. A new dynamic register is proposed to reduce the DAC control delay. To maintain small capacitor arrays, a multiple-reference C-DAC is applied to avoid using a tiny unit capacitance. This prototype ADC consumes a total power of 3 mW from a 1.2-V supply at 400-MS/s. Measured DNL and INL are -0.77/+1.2 LSB and -1/+1 LSB, respectively. The measured peak SNDR and SFDR are 51 dB and 62.3 dB, respectively. The measured ENOB is 8.2 bits, equivalent to a figure-of-merit of 25.5 fJ/conversion-step.