A 48-Gb/s Baud-Rate PAM-4 Receiver With One-Tap Speculative DFE and Reused Comparators

A 48-Gb/s quarter-rate four-level pulse amplitude modulation receiver with a one-tap speculative decision-feedback equalizer and a baud-rate clock and data recovery circuit is presented. By using the time-based technique, 8 comparators and 4 time-based latches are used. The offset voltages of these comparators and the time-based latches are calibrated in the foreground. This chip is fabricated in a 40-nm CMOS process and the active area is 0.1232mm
²
. The power consumption is 85.08mW and the calculated energy efficiency is 1.77pJ/b.