A 14.7-20-Gb/s Reference-Less Baud-Rate CDR Circuit with One-Tap DFE and Time-Interpolation

A 14.7-20-Gb/s reference-less baud-rate clock and data recovery (CDR) circuit with a one-tap decision feedback equalizer is presented. The asymmetrical phase characteristic of the modified Mueller-Muller phase detector (MMPD) is analyzed and utilized for frequency acquisition. The frequency capture range can cover the entire frequency range of the voltage-controlled oscillator. The number of high-speed comparators in the modified MMPD is reduced by using the time-interpolated latch. This quarter-rate CDR circuit is fabricated in 40-nm CMOS technology and its active area is 0.1219
$\text{mm}^{2}$
. For a 20 Gb/s PRBS of
$2^{7}-1$
, the power is 53.4mW and its energy efficiency is 2.66pJ/b.