High-Performance Cascoded CMOS LNA Configuration for Next-Gen Wireless Application

The Low Noise Amplifier is typically the starting stage of an RF receiver. Its main function is to provide enough gain with minimum possible noise. The objective of this work is to introduce an innovative design idea of LNA to obtain improved performance over the traditional design. The LNA Circuit designed here is for Wireless Local Area Network application i.e. 2.4 GHz. The main LNA constraints are Gain, Noise Figure and power consumption. This Paper presents the LNA with Inductive degenerated topology using cascoded dual CMOS architecture for obtaining improved LNA constraints. The LNA design is simulated in the Cadence Virtuoso IC tool using 180nm technology. The results of the simulation show that the gain is 12.35 dB, input return loss (S₁₁) of -6.842 dB, reverse isolation (S₁₂) of -32.9 dB, S₂₂ equals to -0.611 dB. It produces a Noise Figure of 0.281 dB and the corresponding Noise Factor is 1.0068. This proposed LNA circuit operates at supply voltage of 1.8V.