A Pre-Silicon Physical Design Study Towards Mitigating EMSCA on Cryptographic ICs

Electromagnetic side-channel analysis (EMSCA) has recently emerged as one of the most prominent security vulnerabilities in digital cryptographic integrated circuit (IC) design. An abundance of countermeasures have been proposed, but these often incur significant power, performance, and area (PPA) overhead, as well as extra design effort. Additionally, quantifying an IC's EMSCA vulnerability before fabrication remains challenging. This work aims to address the aforementioned issues by presenting a comprehensive IC layout study on an AES-128 encryption engine implemented in 65nm CMOS technology. Our study utilizes an efficient layout and near-field EM simulation framework to quantify the relationship between various PDTs and EM side channel leakage. We demonstrate that a design optimization space exists wherein different layouts which all meet PPA requirements exhibit significantly varying EMSCA vulnerability. We find that small variations in power grid design and standard cell placement can alter the EM leakage of a layout by as much as a factor of three. First-order analyses are found to be insufficient in clearly identifying relationships between layout parameters and leakage; higher-order methods (e.g., deep neural networks) may be needed to assist IC designers in effectively improving security robustness at design time while maintaining PPA and avoiding extra design effort.