Chaotic Technique for High Information Security based on Dual-Hiding Asynchronous-Logic AES Accelerator with High Resistance to Prevent Side-Channel Attacks

In the majority of applications, including e-commerce, online banking, satellite, wireless communications, electronic devices, appliances, signal and digital image processing, etc., data security is regarded as a critical component. Cryptography is a technique which is used to keep the data safe and secret by changing it into a form so that unnecessary users cannot understand. This technique provides a strong, economical way to keep our data as a secret and helps in data integrity verification. Cryptography technique is facing issue from side channel attacks and unable to provide error free data. The proposed accelerator leverages chaotic-based dual-hiding techniques combined with asynchronous logic design to enhance security while maintaining efficiency Chaos-based encryption systems can avoid the difference between power factor (DPA) and differential failure factor (DFA) output by introducing randomness and non-uniformity into the encryption process. Additionally, asynchronous logic design mitigates timing-based side-channel vulnerabilities by eliminating clock signals, thereby disrupting attackers’ ability to extract sensitive information through timing analysis. Also, a chaotic sequence is used in between the process of generating cipher text. Thus, the design will decrease the area overhead and provide strong resistance from side channel attacks and make the system more reliable. The proposed design is executed in Xilinx Vivado 2018.3 and the output is verified using simulation results.