Memristor-Based Phase-Frequency Detector for Phase-Locked Loop Applications

The present paper introduces and illustrates a novel, straightforward Phase-Frequency Detection (PFD) circuit based on two memristor components. This PFD approach can represent the phase or frequency difference between two sinusoidal inputs as a DC signal. As a result, the suggested method does away with the Low Pass Filter (LPF) block in the Phase-Locked Loop (PLL) structure, resulting in a reduction in the dissipated power and overall system area and an increase in the PLL efficiency when employed in many applications such as the communications module of body implants. First, the linear dopant drift memristor model is used to derive a closed-form analytical solution for the proposed PFD concept. Later, simulations for the proposed PFD circuit are carried out utilizing the more realistic nonlinear dopant drift memristor model to verify the validity of the expected findings despite considering all known non-idealities of actually realized memristor devices. The emergence of this circuit will encourage the investigation and development of the first memristor-based PLL system, which can be constructed directly using this Phase detector cascaded by a memristor-based Voltage Controlled Oscillator (VCO), with the latter being extensively researched in the literature.