An Efficient VLSI Architecture of Adaptive Filter for Noise Reduction and Echo Cancellation

Adaptive filter is a concept that is gaining interest in recent years as they start to find practical real-time applications in fields like channel equalisation, echo cancellation, noise cancellation, and a variety of other adaptive
^s
ignal processing applications. This article proposes a VLSI architecture for an adaptive filter application with a control unit that combines noise reduction and echo cancellation techniques. For self-adjustment of the filter weights, the least mean square (LMS) algorithm is utilised. The VLSI implementation and performance analysis provide crucial information about the structure of an algorithm, such as hardware requirements, power consumption, and real-time performance. The performance of the proposed architecture of the adaptive filter is assessed in terms of delay, area, and power dissipation using
$45\ nm$
CMOS technology.