Hardware considerations of a DSP based wireless coded receiver under limited resources

Reliable wireless communication is enabled by adopting advanced Forward Error Correction (FEC) codes, such as Turbo codes. However, the Turbo decoder for real-time communication necessitates accommodating limited resources offered by the DSP processor. This motivates the benchmarking of the Super Harvard Architecture (SHARC) Digital Signal Processor (DSP), which is considered a high flexibility platform. However, implementing turbo code, which is based on the Bahl-Cocke-Jelinek-Raviv (BCJR) algorithm on DSP, requires extensive processing time and high memory usage due to its data dependencies. Motivated by this, the hardware considerations to implement a coded receiver under limited memory and processing time are proposed. A memory management strategy that terminates full memory concerns due to the data dependencies of the BCJR is presented. We show that by jointly optimizing the dynamic memory allocation and accessing the external memory, a significant improvement of the available computing resources and lessen the memory requirements. Results showed that the proposed coded receiver requires a memory size of 21 symbol lengths.