Analysis on the Performance of CNTFET Devices Based on the Impact of CNT Diameter Variation

Currently, the IC industry is facing difficulties to continue scaling down the size of MOSFET technology due its physical limitation. Thus, replacing silicon with carbon nanotube (CNT) may potentially pave a new way to the semiconductor industries because of its small size and better electrical properties. Therefore, this project utilized SILVACO ATLAS software to develop a Gate All-around CNTFET. This software can analyze the electrical behaviors of specified CNTFET structures and provides insight into the internal physical mechanisms associated with the device operation. Hence, the one of the response variables can be extracted such as on-current (I
on
), off-current (I
off
), current ratio (I
on
/I
off
), threshold voltage (Vth), subthreshold slope (SS) and Drain Induced Barrier Lowering (DIBL). In this CNTFET design, the highest current ratio recorded is $7.297 \times 10^6 \mathrm{A}$ when using higher CNT diameter which is 4.0 nm. The larger value of current ratio is contributed by the lowest value of off current which is $4.535 \times 10^{-14} \mathrm{A}$. The 8.0 nm of CNT diameter produced highest on-current with $4.922 \times 10^{-6}$ due to the lowest threshold voltage which is 1.21 V. The 4.0 nm also produced the lowest value of DIBL and SS which is 0.00613 V/V and 0.0613 V/dec respectively. Deeper study on the CNTFET design parameter can significantly affect the device performance because of semiconductor industry demand to have a smaller device technology with better performance. Thus, this study shows that CNT material has the potential to be implemented in the design of FET.