"Approximate Multipliers Based on Low-Power 4:2 Compressors for Error-Tolerant Applications"

Energy-efficient and high-performance general- purpose compute engines, as well as application specific integrated circuits, are highly demanded to facilitate the development of artificial intelligence and big data processing applications. However, with the end of Dennard’s scaling and Moore’s law it is becoming difficult to handle massive amounts of data and complex computations required in these applications. Approximate computing (AC) has emerged as an attractive paradigm in the digital design to address this unprecedented challenge. AC is driven by the observation that many state-of-the-art applications, such as classification, machine learning, data mining, robotics and communication, exhibit error-tolerant characteristics; therefore, a small amount of error (trades off the requirement of exact computation) can be introduced to achieve area, power, and speed benefits. AC techniques can be applied at both the software and hardware layers. At the hardware layer, arithmetic units (multipliers, adders, and dividers) are considered as hardware computational modules. Therefore, the approximation at hardware layer has been focused around the design of approximate arithmetic units. This paper presents approximate multipliers based on novel 4:2 compressors for error-tolerant applications. The proposed 4:2 compressors exhibit zero-mean error behavior while having a comparable hardware utilization with the existing state-of the-art designs. The hardware-efficient as well as the error-efficient designs of variable accuracy-power has been investigated to explore the maximum trade-off. All the designs are synthesized using Cadence Genus synthesis tool (TSMC 65 nm technology) and power is reported using Cadence Joules RTL power solution. A comprehensive error analysis is performed using well-known error metrics such as error distance (ED), mean average distance (MED), mean relative error distance (MRED) and normalized mean error distance (NMED). Moreover, all the designs are also compared with respect to power-delay product (PDP) and MRED to apprehend which designs are lying on the error-energy Pareto- optimal curve. A case study is also presented to demonstrate the applicability of the proposed designs in practical image processing application.