Energy-Efficient Approximate Booth Multipliers for Convolutional Neural Networks

Deep learning algorithms, especially convolutional neural networks (CNN), are being widely used in computer vision applications. In CNN, the processing element (PE) is the basic computational unit that performs convolution operations. An efficient implementation of processing elements in terms of area, speed, and power is required to improve the overall system efficiency. Approximate computing can benefit the hardware implementation of the CNN to limit the usage of hardware resources and attain better performance. For this purpose, in this paper, three designs of approximate Booth multipliers based on hybrid radix-8 encoding are proposed for the multiplication operation in the PE. FPGA-based and CMOS standard cell library-based synthesis are performed. Among proposed designs, hybrid radix approximate Booth multiplier (HR-ABM) achieved 10% LUTs saving and 21% less energy consumption as compared to the already proposed Booth multiplier with sign extension elimination (BMSE). Similarly, synthesis using CMOS standard cell library achieved 35% saving in the area and 43% less energy consumption for HR-ABM. The proposed HR-ABM showed normalized error distance (NMED) of 1.5×10
⁻⁴
and mean relative error distance (MRED) of 0.06×10
⁻²
as the error metrics which are comparable with the state-of-the-art design.