A New Reduced Switch-Count and Balanced Source-Energy Flipped-Ladder Multilevel Inverter Topology

The ability of producing an output voltage with several levels to emulate the desirable sinusoidal waveform has made the Multilevel Inverters (MLI) very popular for their staircase-like output signal, which is then easily filtered to generate a pure sinusoidal with minimum Total Harmonic Distortion (THD). However, this comes at the expense of component count, efficiency and control complexity. The benefits sought after in reducing the number of switches are; savings in overall cost and size of hardware, simplifying the design and reducing number of control signals, in addition to minimizing losses and improving reliability and efficiency of the system. This work introduces a new topology proposing a Flipped Ladder Multilevel Inverter (FLMLI), the merits of which will be compared against the most popular Cascaded Multilevel Inverter (CMLI). The proposed topology focuses mainly on reducing the number of switches compared to conventional CMLI. In addition, the sources will be equally utilized over one switching cycle to guarantee energy balance. This topology will be verified in simulation on 11 levels on the Power Simulation Software platform (PSIM), as well as on Proteus for real hardware emulation verification.