Energy Efficient CNTFET SRAM Cells Using Low Power Techniques

Silicon technology has rapid development, so speed and power dissipation have become significant problems in the nanoscale system. As a consequence, several solutions are available to decrease power consumption and increase the performance of digital systems. This project investigates the performance of the proposed Carbon Nanotube Field Effect Transistor SRAM with the integration of low power approaches such as DTMOS based SRAM cell, LECTOR based SRAM cell, DT_LECTOR based SRAM cell and Drain gating-based SRAM via Cadence Virtuoso (32 nm technology).Drain gating-based SRAM is proposed to provide low power, low latency for write and read operations and more stability in order to address the issue with conventional SRAM and other modern SRAM cells. From the analysis, it is distinguished that the proposed models has reduced the delay by 6.6% and average power is reduced by 12% when compared with the Conventional SRAM cell. All simulation results of the proposed CNTFET 6T SRAM and other models of low-power CNTFET SRAM have been performed in 32 nm CNTFET technology using Cadence Virtuoso.