Application of Sampling in Industrial Analog Defect Simulation

In this paper, practical usage methodology of sampling technologies in industrial analog circuits is presented. We provide answers to common questions - e.g., how to select sample size, how to verify accuracy of sampling algorithms, and what savings may be achieved by using sampling technologies - by means of running a state-of-the-art commercial analog defect simulator on a few recently provided, industrial-sized analog circuits. We demonstrate our recommended flow and present results for a PLL, a SARADC, and a PHY circuit - with transistor counts ranging approximately between 3000 and 30000.