Compression-Aware ATPG

The remarkable growth of the circuit size and complexity is primarily due to the advances of VLSI design and manufacturing technologies. The on-chip linear sequential test compression has become the de facto industrial mainstream DFT methodology in reducing the overall cost of testing large chips. In this paper, we propose a novel and efficient compression-aware ATPG method to significantly boost the performance of ATPG and reduce pattern count. The proposed approach first analyzes the intrinsic dependency of the equations determined by a linear sequential decompressor to build Maximal Linear Independent Group (MLIG). Next it computes the implied values given ATPG generated test cubes based on MLIG. The implied values can significantly improve the test compaction and reduce the ATPG run time due to the reduction of value conflicts between ATPG and compression. The proposed approach does not affect test coverage, requires no extra hardware support, and can be applied to any linear sequential compression scheme. Experimental results on several industrial designs demonstrate that on average the proposed approach can reduce the number of ATPG patterns by 7.57% and the ATPG run time by 28.4%.