A 6 Gbps PAM-3 Transceiver with Time-Varying Offset Compensation

The advancements in CMOS technology have increased the data rate of the memory interface. CMOS technology scaling improves performance by reducing supply voltage, parasitic capacitor, and physical area. Thus, device reliability issues, such as component mismatches and aging effects become prominent in the aggressively scaled technology. However, because sensing the characteristics of analog circuits is difficult, previous works have focused on digital circuits of the transceivers [1]. Further, many studies have presented pulse amplitude modulation (PAM) such as PAM-3/4 for bandwidth extension [2] [3]. However, the signal levels of PAM are highly susceptible to PVT variations, component mismatches, and aging effects. Therefore, any offset in the front-end degrades the signal integrity significantly. Therefore, this paper proposes an offset compensation technique for a PAM-3 transceiver. The proposed technique detects prohibited data patterns and generates optimal reference voltage to cancel out the offset.