Hardware Minimization of Two-Level Adiabatic Logic Based on Weighted Maximum Stable Set Problem

Adiabatic logic circuit can be considered as one of the most attractive solutions for low power circuits. This paper treats a design optimization of Two-Level Adiabatic Logic (2LAL) circuit which has a relatively simple structure and an excellent low-power performance compared with many other asymptotically adiabatic or quasi-adiabatic logic families, while it needs a large number of timing buffers for "decomputation". We focus on "early decompute" technique for fully pipelined 2LAL, and proposes an ILP approach to the optimization of early decompute for minimizing hardware cost. First we show that our hardware minimization problem can be reduced into "Stable Set" problem, and then we derive its ILP formulation. The superiority of the proposed method is evaluated using ISCAS-85 benchmark circuits.