A High Linearity Class AB Power Amplifier for Sub-1 GHz Applications

In this paper, a 400MHz class-AB power amplifier (PA) with high linearity and output power is presented. This two-stage PA consists of on-chip power transistors and off-chip tunable LC load networks for reducing the chip cost due to the low operating frequency. Based on the linearity-oriented optimization of matching networks, the iterative circuit/EM co-simulation of the integrated circuit, package, and PCB levels is accomplished to minimize the discrepancy between the simulation and measurement results. The design is implemented in 130 nm CMOS technology with a core area of 0.13 mm
²
. Measurement results show that the PA delivers an output 1-dB compression of 18.1 dBm under 2.5 V voltage supply. Moreover, it achieves a saturated power of 24.2 dBm with a maximum gain of 27.8 dB and power-added efficiency (PAE) of 43.8%.