3D IC Design-for-Test with Implementation of the IEEE 1149.1-2013, the IEEE 1500-2005, and the IEEE 1838-2019 Standard

The paper presents a design for a testable 3D integrated circuit (IC), and more specifically the Design-for-Test (DfT) method of its stacked layers. It describes how it implements the IEEE 1149.1-2013 Standard, the IEEE 1500-2005 Standard, and the IEEE 1838-2019 Standard. Finally, it presents the instructions that allow for the combined implementation of these Standards, and an analysis of its additional required footprint.

I. Introduction

To maximize the benefit of Circuit Integration, 3D ICs and their microscale Through-Silicon Vias (TSVs) were introduced as a new inter-die connection. Even though they suffer from both area and electrical coupling overhead, they are a key technological advancement for die connectivity. Testing is of paramount importance when it comes to TSVs, as their high integration density, and their manufacturing process, make them especially vulnerable to various defects. Therefore, effective defect screening and quality assurance are not only necessary but also a prerequisite for 3D ICs.