A ReRAM-based Nonvolatile FPGA

Modern challenges in electronics engineering include the need for massive scale computation devices that are energy-efficient. Conventional digital memory devices such as static random-access memories (SRAMs) and dynamic random-access memories (DRAMs) are volatile and require continuous power supply to retain its data or interval refreshes even when the cell is not selected. These ‘non-use’ power consumption scenarios massively contribute to power inefficiency in large-scale arrays. In this work, nonvolatility is introduced to the field-programmable gate array (FPGA), an integrated circuit capable of parallel computation. The nonvolatile (NV) FPGA (nvFPGA) is achieved through novel resistive random-access memory (ReRAM)-based designs of three major components in the FPGA architecture, the lookup table (LUT) and the D flip-flop (DFF) inside the configurable logic block (CLB) and the switching blocks (SwBs) responsible for interconnect routing. The nvFPGA successfully demonstrates NV with the NV CLB having a 73.463% higher path delay during WRITE and a 92.206% lower path delay during READ compared to the conventional volatile CLB. The NV SwB shows higher WRITE and READ delays compared to the conventional volatile switching block (SB). However, its function in the FPGA is to store routing configuration bits and there is only a one-time WRITE into the nvSB during initial programming.