Design and Implementation of Radix-4 MBW Multiplier using 45 nm technology

A novel high performance, low power MBW Radix-4 multiplier unit is proposed in this study. Dynamic voltage scaling has been used to accomplish the low power performance. The proposed multiplier unit was built using three different low power techniques: a drop in output capacitance and switching activity, as well as a decrease in biassing voltage, based on the CCGDI technique, which lowers output capacitance and switching activity. Here, the Wallace tree counters use parallel adders based on GDI to reduce the delay and number of transistors. The multiplier has been created utilizing constant threshold voltage PTM 45 nm devices technology and modelled in a traditional CAD tool simulator for multiplications of 4, 8, and 16-bit operands. The proposed design uses an average of 238.98 l W of power. In terms of the power-delay product, it does 16 × 9 x 16 bit multiplications at a speed of 100 Mbps with a propagation latency of 2.458 ns, which is 47% quicker than the counter-based GDI Wallace tree multiplier structure.