FPGA Implementation of Morphological Gradient Operation using Xilinx System Generator

This paper presents the hardware implementation of morphological gradient algorithm on Field Programmable Gate Array (FPGA) platform using Xilinx System Genrator (XSG). Morphological operations are one of the most popular and widely used tools in image processing and analysis due to its flexibility and low design complexity. However, these operations incur additional processing time since they perform repetitive calculations on pixels with varied image dimensions. Thus, hardware implementation is required in order to increase the speed-up and the performance. XSG is a powerful simulink tool that provides hardware specific optimized Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL)/Verilog code for a design using Xilinx block set. A pipelined architecture is designed by making use of block sets which is synthesized and implemented on Zynq FPGA device. The results of the proposed implementation show significant performance improvement over other existing designs.