Implementation of Parity Generator and Checker using Quantum-Dot Cellular Automata

In this day and age of advanced digital technologies, devices with very low power consumption are seeking attention. In QCA nanotechnology, the logic circuits are designed to be incredibly dense and consume very little power. This capacity of QCA is the best alternative to CMOS technology. As the QCA technology can be used in nano circuits, the rectifying and error detection can be done in communications for the received signals. Particularly in error detection and data transmission, parity generators and checkers are the major part in the central processing unit. The use of an XOR gate to generate 3-bit and 4-bit parity generators and checkers is proposed in this study and simulation is performed with QCAD tool along with analysis of power dissipation using QCADE.