A comprehensive study of alignment, overlay and leveling in throughput effect under PEP-align for high volume manufacturing fab immersion group

In recent years, advances in semiconductor technologies have resulted in continuous shrinkage of the process window required to fabricate a device, and specifically, the shrinkage of the overall overlay budget of the immersion layers, especially in DRAM overlay requirement tighter than others for array design. A key contributor of overlay variations is scanner alignment strategy and alignment overall mark counts and model. In high-volume manufacturing (HVM), the reduction in alignment mark count can get productivity improvement, however, that tradeoff impacts the scanner alignment layout, model and in production overlay performance. In this case, ASML provide the PEP-align solution in NXT1980Di through leveling scan model change from LDL to LIL then lead more budget time in M-side. Therefore, there will be more alignment mark and model selection possibility. According to this, we present a comprehensive study of an in-line production experiment and simulation results to evaluate overlay performance with PEP-align option for alignment mark, alignment model and throughput behavior relationship.