An Energy-Efficient Conditional-Boosting Flip-Flop with Conditional Pulse for Low Power Application

Along with size and performance considerations, power consumption is regarded as a significant challenge in current VLSI design. In digital systems, the flip flop is an extremely significant clocked timing element. An energy-efficient conditional-boosting flip-flop with a conditional pulse is proposed for low power applications. The proposed flip-flop allows voltage - boosting to achieve low delay. It allows conditional capture to reduce switching power consumption by removing unwanted boosting operations. It also allows conditional pulse generation to eliminate unwanted pulses resulting in less switching power consumption. Simulation results in a 90-nm CMOS technology represented that the proposed flip-flop delivered up to 34% lower delay and 53% better energy-delay product at 25% data switching activity compared with the conventional conditional-boosting flip-flop.