An Optimized FPGA Architecture for GPS Signal Acquisition

GNSS signal acquisition is a 2-dimensional search process of finding an approximate estimate of code phase, and Doppler. There are techniques available in the literature to search one of the dimensions in parallel to reduce the mean acquisition time. Further continuous efforts are made to search both dimensions in parallel or quasi-parallel. In this paper, an Optimized FPGA architecture of the GNSS acquisition engine is proposed. Compared with other direct acquisition structures, the search efficiency of the acquisition engine is improved by implementing a quasi-parallel code phase and parallel frequency-domain technique. The proposed architecture can be scaled to parallel code phase and parallel frequency-domain technique. Using the Optimized technique implemented in this paper, the search time reduces to 0.256 seconds as compared to 1.1 seconds in a similar quasi-parallel code phase and parallel frequency-domain technique. The proposed architecture is highly resource-efficient. Proposed architecture is implemented for modernized GPS-L1C signal