Efficient ECC Architecture for Data Storage Memory Applications

In this wireless environment when a message is transmitted the information gets corrupted due to inter symbol interference and noise. The information also gets corrupted due to scaling of memory devices, hence the efficiency of the transmission decreases due to the corruption of the data. The error correction techniques process the received data which are temporarily stored in memory. Memories like SRAM and DRAM memory cells will store the data temporarily before processed by Error Correction Codes (ECCs). In this paper an efficient architecture for 2-D BCH ECC of size 15 x 15, with an error correction capability of 2 x 2, in the frequency domain are developed. The 2-D BCH encoder is designed and implemented using the conjugate class properties of finite fields to a reduction of number of gates. With the help of Inverse Discrete Finite Field Fourier Transform (IDFFFT) and Discrete Finite Field Fourier Transform (DFFFT) the data is converted from frequency domain to time domain and wise versa. The modified 2-D BCH decoder is designed with the help of Modified BM algorithm to reduce the resource utilization. The results of the encoder and decoder are illustrated in this paper. The proposed Modified Berlekamp's Massey (MBM) algorithm utilizes 77.3% lesser LUT's and 65.82% of dynamic power consumption lesser compared to Berlekamp's Massey (BM) algorithm. The proposed architecture is suitable for power and area efficient memory applications.