A 0.95-to-5.28 GHz Fast Locking and Power Efficient Digital Phase Locked Loop

Computers, radios, televisions, and mobile phones are only a few examples of devices that depend on phase-locked loops (PLLs). PLL development is an extraordinarily complex process as it involves different parameters, and it is difficult to optimize all these parameters to get better performance. Depending on the application in which the PLL is used, we tend to improve some issues at the expense of others. The proposed Digital PLL (DPLL) is designed with a current-controlled ring oscillator (CCRO) which consumes low power and has a small locking time and operates over a wide range compared to other Digitally Controlled Oscillators (DCOs). The proposed architecture is implemented in a TSMC 65 nm CMOS process. It can generate an output frequency from 0.95 to 5.28 GHz and operates across a supply voltage range of 0.6 V to 1.2 V. At 0.9 V supply voltage the output frequency is about 3.091 GHz and the PLL consumes 50.3 μw with locking time 79.3 ns.