A Fast Offset Reduction Loop Based on a Bilinear Integrator for Sensor Readout Circuits

An offset reduction loop (ORL) is an efficient technique to remove large offset in systems with high gain, for example sensor readout amplifiers. In this paper a new ORL is proposed that is based on an analog bilinear integrator. We show that this introduces an additional level of freedom in designing and accurately controlling the shape of the overall system's transfer function. Advantages of this ORL include the freedom to set the notch bandwidth of the ORL based on the 1/f-noise corner frequency. The ORL can thus be made fast enough to be able to remove 1/f-noise up to the 100 kHz range and even beyond. A prototype of the proposed ORL is applied to a Hall plate readout based on an in-the-loop sampling amplifier (ILSA) and implemented in
$0.18\,\mu\mathrm{m}$
CMOS. The measurements on the experimental chip confirm that the transfer function behaves as expected.