A Novel Design Methodology for Low-Power, Low-Noise LC-Based Digital-Controlled Oscillators

This work presents a design methodology for LC-based oscillators that optimizes the phase noise/power trade-off. The proposed methodology takes into account from early design stages the effects of the degradation of the quality factor of both the inductor and varactors. Based on this, the limits of the design space and the minimum power consumption that fulfill targeted specification are determined. This methodology has supported the design of a 26.6-GHz digital-controlled oscillator. Post-layout simulations in a TSMC 28-nm CMOS RF process show a phase noise of −102.1 dBc/Hz at 1-MHz offset with 1.25-mW power consumption for 1.0 V under typical conditions. This results in a FOM of 189.6 dBc/Hz at 1-MHz offset frequency.