Design and Simulation of Peripheral Driving Circuitry for Computational ReRAM

As an alternative approach to the von Neumann architecture, the notion of computational resistive random-access memory (ReRAM) has emerged, promising faster and more energy-efficient computing systems. In this context, we present a classification of ReRAM-compatible logic design strategies and highlight the potential of nonstateful ratioed logic for computational ReRAM modules. We provide insights towards the design of ad-hoc peripheral circuitry that allows the fusion of memory and ratioed logic operations in the ReRAM module in a reliable manner; i.e., the driving/sensing circuitry allows carrying out memory operations and in-memory multilevel ratioed logic operations. To this end, we present in detail a computational ReRAM driver and focus our description on the operational features that enable memory/logic operations in every row of the crossbar array. We validate circuit functionality through LTSpice simulations for read/write memory and logic operations using a threshold-type bipolar ReRAM device model. The presented practical solutions contribute to the viable development of computational ReRAM.