Speeding up FPGA Prototyping on Space Programs with HLS Workflow. Use Case: Video Compression On-board Satellites

The complexity of electronics systems has increased in the last years, which is mainly motivated by the computational capabilities offered by technologies such as FPGAs and SoCs. This requires a change of paradigm in the design methodology, since traditional workflows based on RTL descriptions can prolong in excess the development and verification time when the complexity of the design increases. This is a bottleneck for certain applications, such as the space industry, where mission programs are hardly constrained and delays are not allowed. This work analyses the alternative of following the High-Level Synthesis methodology, which allows to reduce both design and verification time. In addition, prototyping is also accelerated and a design space exploration of complex hardware architectures can be performed at early stages of the design flow. As use case to demonstrate the viability of following this design methodology, a video compression chain based on the CCSDS 123.0-B-2 standard is fully developed in HLS and implemented on FPGA. The designed compression chain is detailed, including the directives inserted to optimize the design. Finally, the test set-up employed for the validation on a Xilinx Kintex UltraScale XCKU040 FPGA is explained and some preliminary results are presented in terms of resources utilization and frame rate, accomplishing the objectives defined in the H2020 VIDEO project.