MIS Strip Warpage Improvement By FEA Study

Molded interconnect substrate (MIS) is a low profile fine pitch packaging that built on a leadframe substrate. It resembles a fan-out wafer package but with limited I/Os (about 150 to 200 I/OS) and densities. It consists of one or more layers of premolded structure with each layer consists of copper traces or interconnects embedded in mold compound to provide electrical connections. Packaging house then use that substrate and assembles an IC package around it. MIS package offers better space and routing capabilities for electrical performance and smaller form factors against traditional QFN or leadframe based packages. Comparing to conventional molding on substrate, using mold compound as dielectric layer or substrate can have better thermal process performance owing to more compatible properties with package encapsulation material and hence less thermal expansion mismatch. Besides, MIS is an alternative to organic laminate substrate but cheaper due to its escapee of micro via drilling process cost. Its coreless substrate can offer ultra-low inductance between layers to benefit higher speed connections. The emerging technology is now being leveraged in the high power and high thermal IC applications. The disadvantage of MIS is it is limited to around 25 um width and pitch of metal trace and is geared for mainly mid range applications. The major challenge is the coreless substrate is thin and prone to warpage and uniformity issues during a process and hence high probability of lower yield. The primary goal of this paper is to derive a solution that capable of reducing strip warpage and hence reducing tensile stress in chips (for eliminating potential cracked die issue) during wire bond process through finite element modeling.