A CMOS Compatible In-sensor Computing Neural Network with Gate/Body-Tied PMOSFET Array

This paper presents a new in-sensor computing neural network with a CMOS compatible photodetector, Gate/Body-Tied PMOSFET (GTP). The GTP array realizes the in-sensor computing architecture in a compact way with standard CMOS process. TCAD simulation and image recognition tasks have been performed to evaluate the practicability and accuracy. The array demonstrates good tunability and scalability for low latency computing applications, such as real-time video analysis.

1. Introduction

The rapid increase of sensor nodes in modern sensory networks brings new challenges for sensor and processing platform design. To achieve real-time applications such as real-time video analysis, ultrafast sensors and neural networks should be implemented. Under this circumstance, in-sensor computing has been purposed, where part of the computing task is embedded in the sensor array and the processing time for the sensor and the neural network has been significantly reduced [1]. A conventional sensor array and an in-sensor computing array are shown in Fig. 1. Since the workload for the Analog-to-Digital Converter (ADC) between the sensor array and computing unit is reduced and the responsivity of each sensor acts as the weight for the neural network. The time to get output from the neural network is very short.