An Ultralow Loss Insulated Gate Bipolar Transistor with a Punch-Through NPN Transistor

An ultralow loss insulated gate bipolar transistor (IGBT) is proposed and numerically investigated in this paper. A punch-through NPN transistor is introduced to clamp the potential of the carrier stored layer CS-layer. Consequently, the doping concentration of the CS-layer could be increased interminably to reduce the on-state voltage without affecting the breakdown capability. And a 62% reduction in turn-off loss could be achieved at the same on-state voltage. Besides, owing to the potential of the floating P-well region is also clamped, the gate self-charging effect is significantly suppressed. As a result, the lower limit of the maximum reverse-recovery dV/dt of the freewheeling diode can be reduced by 64.3% when compared with the IGBT with the floating P-well region.