Phenomenon and Mechanism Investigation of the Cryogenic Random Telegraph Noise for 18 nm FDSOI CMOS

In this work, we investigate the cryogenic random telegraph noise (c-RTN) for 18 nm n- and p-FETs on the FDSOI substrate, to study the impact of temperature on the trapping/de-trapping mechanisms for the FDSOI CMOS. As compared with p-FETs, n-FETs exhibit more complicated and severe c-RTN characteristics at certain bias conditions for their higher interface trap level. The capture τ
c
/emission τ
e
time constants were extracted at various temperatures to compare the trapping/detrapping mechanisms at different temperature regions. The shorter and V
G
-independent time constants confirm that trap tunneling is the dominant RTN source for the cryogenic drain current variation. The severe c-RTN with higher magnitude and switching frequency should be considered and modeled in the cryogenic circuit design.