An op-amp for 12bit 1.25GS/s pipelined ADC with negative impedance compensation in 65nm CMOS

This paper proposed an op-amp with negative impedance compensation for high speed and high resolution pipelined ADC. In the circuit implementation, a continuous-time common-mode feedback circuit base on source follower is used to ensure the reliability of the 2.5V power supply op-amp, and this circuit is also reused to achieve the negative impedance compensation to expand the bandwidth and increase the gain of the op-amp without additional circuit. Simulation results shows, the op-amp’s loop gain is about 70dB, and the loop bandwidth reaches 4GHz which meet the 12bit 1.25GS/s’ design indicators. Under the same current consumption, compared with the op-amp which without negative impedance compensation, the loop gain is increased by about 10dB, and the loop bandwidth is increased by about 300MHz.