Current Uniformity Optimization of Multi-Chip SiC Module for High-Power Applications

In high-power applications, paralleled connections for multiple SiC MOSFETs suffer rigorous demands on the current uniformity. 1200V/900A SiC power module with 16 chips paralleled is investigated to achieve high power rating. The mechanism of electromagnetic coupling between SiC MOSFET chips is analyzed. The stray inductance reduction due to eddy current phenomenon is revealed. In order to achieve uniform current for paralleled chips, DBC separation, terminal pin centralization and chip location adjustment need to be considered. Based on the analysis of the mismatched stray inductance in the equivalent circuit, the optimization method of symmetry and mirroring is proposed. In addition, the effective current area of the terminal lamination is improved. Furthermore, the effect of die orientation on the current uniformity is also analyzed. Finally, double-pulse characterization results for the SiC power module at 700V/900A of the optimized structure verifies the effectiveness of the current uniformity.