Micro-Latchup Location and Temperature Characterization in a 7-nm Bulk FinFET Technology

Location and temperature characteristics of micro-latchups at the 7-nm bulk FinFET technology are investigated through thermal images. Thermal images show that micro-latchups are induced at random locations when tap cells are placed evenly across the die. Inducing multiple micro-latchups on the die results in clustering of micro-latchups and significant increase in IC-level current and local temperature on the die. Micro-latchups become eliminated serially when the supply voltage is reduced but kept above the holding voltage. Subsequent increase in supply voltage reinitiates micro-latchups on the IC. Temperature within a micro-latchup region shows an increase from room temperature to as high as 140 °C. These results show clustering of micro-latchups are a serious reliability threat at the 7-nm FinFET node.