Implementation of a 4*4 10T SRAM Array using Domino Schmitt Trigger

As the CMOS technologies are growing, the importance of portable devices like sram are also increasing. SRAM is one of the important part of cache. It is used in many applications such as microprocessors where it occupies a large portion of and also consumes a huge of energy. It is proven that memories play a significant role in power and delay related issues occurring in the system. This paper aims at designing a low power consuming SRAM cell. Domino Schmitt trigger is introduced in to the conventional SRAM circuit for reducing its consumption of power. The modification is done in 9T and 10T conventional SRAM circuit. Power, delay, power delay product and noise margin of the conventional and modified SRAM cells are calculated and compared. Alongside 4X4 SRAM array of modified 10T is designed. The PDP of 9T is reduced by 12.37% and for 10T by 7.44%.