Investigation of Switching and Figure of Merits in New Charge Balanced n-Vertical Trench Epilayer p⁺ -Shield Super Junction Accumulation Mode MOSFET

In this work, we have simulated a charged balanced new vertical Trench Epilayer p⁺ -Shield Accumulation Mode MOSFET device (SJnVTEpSPMOS) with Super Junction in its drift region. This modifies the tradeoff relation between RON and Breakdown voltage (BV) using ATLAS 2-D numerical simulation incorporating different physics models, breaking the traditional Silicon Limit. Our proposed device has the gate and drain well isolated due to the presence of p⁺ -shield at the bottom of the Trench, Also the channel is inaccessible from the super junction drift layer. The proposed device shows a significant outcome in term of Breakdown voltage, switching and FOM comparing with the Conventional Accumulation Mode MOSFET. We get high breakdown voltage of 31. 0v, Gate to drain charge value as low as 23.6 pC, FOM of 22.65 m$\Omega$.nC with device cell pitch of 3$\mu$. Our further simulation study shows a significant decrease in Gate to drain Capacitance. We have introduced for the first time the advantage of vertical n Epilayer with lateral (horizontal) p⁺ -shield along with Super Junction in drift region, with great improvement in both Baliga’s FOMs.